The present invention relates generally to electronic circuits including a phase to digital converter, and more particularly to a digital phase-locked loop (PLL) with a phase to digital converter.
A PLL is a control system useful in electronic devices such as radios, computers, telecommunication equipment and the like. The PLL contains a phase frequency detector (PFD) and a controlled oscillator, and traditionally is constructed using a combination of both digital and analog circuitry. The PFD compares the frequencies of an input reference clock and a feedback clock and generates a phase difference of the two input frequencies as an output. If the two input frequencies differ, the PFD generates a periodic output proportional to the difference of frequency/phase. If the reference clock frequency differs from the feedback clock frequency, a phase-error signal is generated and filtered and used to cause the feedback clock to shift and lock-in to maintain the input reference clock frequency.
Since the advent of deep sub-micron technologies (e.g., elements 100 nm and smaller), digital circuits have been replacing the analog components of a PLL. Digital PLLs are becoming more attractive because they can be made with compact digital filters that replace bulky and leaky capacitor and resistor based analog loop filters, and the leakage and current mismatch prone charge pump of an analog PLL is not required in a digital PLL. Additionally, noise susceptible analog control of the controlled oscillator in an analog PLL can be replaced with inherent noise immune digital control for the controlled oscillator in a digital PLL. Thus, in a digital PLL, the phase error information is processed in the digital domain. The phase difference between the reference clock and the feedback clock is digitized and processed by a digital filter, which controls the oscillator frequency.
However, existing PLLs that are completely digital provide phase to digital converter outputs at each rising edge of the reference clock based on the phase difference information obtained from the previous reference clock cycle and therefore, phase correction is delayed by one reference clock cycle. That is, conventional fully digital PLLs correct phase error for the previous phase difference between the reference clock cycle and the feedback clock cycle.
Therefore, a faster output phase to digital converter is needed for faster correction of phase error information by a digital PLL.